EPM3256ATC144-10N

Product Summary

The EPM3256ATC144-10N is a High-performance, low-cost CMOS EEPROM-based programmable logic device. The EPM3256ATC144-10N is based on the Altera MAX architecture. Fabricated with advanced CMOS technology, the device operates with a 3.3-V supply voltage and provide 600 to 10,000 usable gates, ISP, pin-to-pin delays as fast as 4.5 ns, and counter speeds of up to 227.3 MHz. The EPM3256ATC144-10N architecture supports 100% transistor-to-transistor logic (TTL) emulation and high-density small-scale integration (SSI), medium-scale integration (MSI), and large-scale integration (LSI) logic functions.

Parametrics

EPM3256ATC144-10N absolute maximum ratings: (1)Supply voltage:–0.5 to 4.6V; (2)DC input voltage:–2.0 to 5.75V; (3)DC output current, per pin:–25 to 25mA; (4)Storage temperature:–65℃ to 150℃; (5)Ambient temperature:–65℃ to 135℃; (6)Junction temperature:135℃.

Features

EPM3256ATC144-10N features: (1)Built–in boundary-scan test (BST) circuitry compliant with IEEE Std. 1149.1-1990; (2)Enhanced ISP algorithm for faster programming; (3)ISP_Done bit to ensure complete programming; (4)Pull-up resistor on I/O pins during in–system programming; (5)High–density PLDs ranging from 600 to 10,000 usable gates ; (6)4.5–ns pin–to–pin logic delays with counter frequencies of up to 227.3 MHz; (7)MultiVoltTM I/O interface enabling the device core to run at 3.3V, while I/O pins are compatible with 5.0–V, 3.3–V, and 2.5–V logic levels; (8)Pin counts ranging from 44 to 256 in a variety of thin quad flat pack (TQFP), plastic quad flat pack (PQFP), plastic J–lead chip carrier (PLCC), and FineLine BGATM packages; (9)Hot–socketing support; (10)Programmable interconnect array (PIA) continuous routing structure for fast, predictable performance; (11)Industrial temperature range; (12)PCI compatible; (13)Bus–friendly architecture including programmable slew–rate control; (14)Open–drain output option; (15)Programmable macrocell flipflops with individual clear, preset, clock, and clock enable controls; (16)Programmable power–saving mode for a power reduction of over 50% in each macrocell; (17)Configurable expander product–term distribution, allowing up to 32 product terms per macrocell; (18)Programmable security bit for protection of proprietary designs.

Diagrams